1. Field of the Invention
The present invention relates to a semiconductor device including a memory macro and fuse box and, more particularly, to a method of transferring fuse data in a semiconductor memory. For example, the present invention is applied to a dynamic memory.
2. Description of the Related Art
In a semiconductor memory, redundancy information is stored in a nonvolatile manner in an optical fuse (to be referred to as an o-fuse hereinafter) or an electrical fuse (to be referred to as an e-fuse hereinafter) formed in a chip. In addition to the redundancy information, trimming data for adjusting the internal power supply and internal timings and the chip ID as the fabrication log of the semiconductor memory are also stored as fuse data.
The o-fuse is made of a material such as a metal, and cut by, e.g., irradiation with a laser. Therefore, no interconnections can be formed near the o-fuse and in the layers above and below it, so interconnections cannot be efficiently formed. In an embedded memory including various circuits such as a memory macro, memory controller, and MPU, for example, it is often desirable to form interconnections for connecting these circuits over the memory macro having a large area. If o-fuses are scattered on the memory macro, however, interconnections to be formed over the memory macro are limited. This makes it impossible to efficiently form interconnections in the embedded memory as a whole.
Accordingly, an arrangement (so-called fuse box) is proposed in which o-fuses or e-fuses are not formed in the memory macro but collectively formed in one portion outside the memory macro. The fuse box has the advantages that upper interconnection layers above the memory macro can be freely formed, and the cutting efficiency of the o-fuse increases and the fuse cutting time shortens because the fuses are gathered in one portion. The cutting efficiency increases even when e-fuses are gathered in one portion.
The fuse data described above must be transferred serially by connecting latch circuits scattered in the memory macro in series. Since the fuse data is transferred to and saved in the latch circuits in synchronism with transfer clocks, the numbers of the transfer clocks, fuse data, and latch circuits must be equal.
On the other hand, it is sometimes favorable to branch the latch circuits in the memory macro, instead of serially connecting them as a fuse data transfer path. For example, this arrangement is desirable when the power supply voltages of row-redundancy latch circuits and column-redundancy latch circuits in the memory are different. However, this arrangement has the problem that a level shift circuit must be inserted in each space between the latch circuits in the transfer path formed by serially connecting them. Also, branching the transfer path is sometimes more convenient than the serial transfer performed by connecting the latch circuits in series, depending on the limitations on the layout.
Unfortunately, the above conventional method serially transfers the fuse data by using the transfer clocks equal in number to the latch circuits. Since a number of transfer paths are simultaneously driven, the power consumption increases. In addition, the fuse data transfer paths cannot be branched. If the transfer paths branch, the numbers of fuse data and clocks transmitted to each latch circuit are no longer equal. This makes it impossible to accurately stop each data in a latch circuit where the data is to be latched at the end of data transfer.
Note that Jpn. Pat. Appln. KOKAI Publication No. 2003-222656 discloses a semiconductor integrated circuit device including a high-performance test clock generator capable of a timing margin testing operation. In this semiconductor integrated circuit device, the test clock generator including a register sequential circuit and clock output controller is formed between a pulse generator and logic circuit. If a testing operation is found to be valid, the transmission of clock pulses generated by the pulse generator to the logic circuit is stopped, and the register sequential circuit controls the clock transmission controller in accordance with register setting information, thereby outputting clock pulses for operating the logic circuit by using a pulse signal generated by the pulse generator.